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Results: 1-7 |
Results: 7
FAULT-TOLERANT ALGORITHMS FOR BROADCASTING ON THE STAR GRAPH NETWORK
Authors: LO NW CARLSON BS TAO DL
Citation: Nw. Lo et al., FAULT-TOLERANT ALGORITHMS FOR BROADCASTING ON THE STAR GRAPH NETWORK, I.E.E.E. transactions on computers, 46(12), 1997, pp. 1357-1362
PARALLEL EVENT-DRIVEN LOGIC SIMULATION ALGORITHMS - TUTORIAL AND COMPARATIVE-EVALUATION
Authors: BAKER WI MAHMOOD A CARLSON BS
Citation: Wi. Baker et al., PARALLEL EVENT-DRIVEN LOGIC SIMULATION ALGORITHMS - TUTORIAL AND COMPARATIVE-EVALUATION, IEE proceedings. Circuits, devices and systems, 143(4), 1996, pp. 177-185
A UNIFIED ALGORITHM FOR THE ESTIMATION AND SCHEDULING OF DATA-FLOW GRAPHS
Authors: HU Y CARLSON BS
Citation: Y. Hu et Bs. Carlson, A UNIFIED ALGORITHM FOR THE ESTIMATION AND SCHEDULING OF DATA-FLOW GRAPHS, Journal of circuits, systems, and computers, 6(3), 1996, pp. 287-318
DUEL EULERIAN PROPERTIES OF PLANE MULTIGRAPHS
Authors: CARLSON BS CHEN CYR MELIKSETIAN DS
Citation: Bs. Carlson et al., DUEL EULERIAN PROPERTIES OF PLANE MULTIGRAPHS, SIAM journal on discrete mathematics, 8(1), 1995, pp. 33-50
A PREPROCESSOR FOR IMPROVING CHANNEL ROUTING HIERARCHICAL PIN PERMUTATION
Authors: CHEN CYR HOU CYC CARLSON BS
Citation: Cyr. Chen et al., A PREPROCESSOR FOR IMPROVING CHANNEL ROUTING HIERARCHICAL PIN PERMUTATION, IEEE transactions on computer-aided design of integrated circuits and systems, 14(7), 1995, pp. 896-903
LILA - LAYOUT GENERATION FOR ITERATIVE LOGIC-ARRAYS
Authors: WU QH CHEN CYR CARLSON BS
Citation: Qh. Wu et al., LILA - LAYOUT GENERATION FOR ITERATIVE LOGIC-ARRAYS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(11), 1995, pp. 1359-1369
DELAY OPTIMIZATION OF DIGITAL CMOS VLSI CIRCUITS BY TRANSISTOR REORDERING
Authors: CARLSON BS LEE SJ
Citation: Bs. Carlson et Sj. Lee, DELAY OPTIMIZATION OF DIGITAL CMOS VLSI CIRCUITS BY TRANSISTOR REORDERING, IEEE transactions on computer-aided design of integrated circuits and systems, 14(10), 1995, pp. 1183-1192
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