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Results: 1-3 |
Results: 3
Analog VLSI hardware implementation of a supervised learning algorithm
Authors: Bo, GM Caviglia, D Chible, H Valle, M
Citation: Gm. Bo et al., Analog VLSI hardware implementation of a supervised learning algorithm, STUD FUZZ S, 74, 2001, pp. 193-217
A circuit architecture for analog on-chip back propagation learning with local learning rate adaptation
Authors: Bo, GM Caviglia, DD Chible, H Valle, M
Citation: Gm. Bo et al., A circuit architecture for analog on-chip back propagation learning with local learning rate adaptation, ANALOG IN C, 18(2-3), 1999, pp. 163-173
Analog VLSI on-chip learning neural network with learning rate adaptation
Authors: Bo, GM Caviglia, DD Chible, H Valle, M
Citation: Gm. Bo et al., Analog VLSI on-chip learning neural network with learning rate adaptation, KLUW S ANAL, 512, 1999, pp. 305-330
Risultati: 1-3 |