AAAAAA

   
Results: 1-3 |
Results: 3
DESIGN TECHNIQUES FOR FAULT-TOLERANT SYSTOLIC ARRAYS
Authors: ESONU MO ALKHALILI AJ HARIRI S ALKHALILI D
Citation: Mo. Esonu et al., DESIGN TECHNIQUES FOR FAULT-TOLERANT SYSTOLIC ARRAYS, Journal of VLSI signal processing, 11(1-2), 1995, pp. 151-168
AREA-EFFICIENT COMPUTING STRUCTURES FOR CONCURRENT ERROR-DETECTION INSYSTOLIC ARRAYS
Authors: ESONU MO ALKHALILI AJ HARIRI S
Citation: Mo. Esonu et al., AREA-EFFICIENT COMPUTING STRUCTURES FOR CONCURRENT ERROR-DETECTION INSYSTOLIC ARRAYS, Journal of VLSI signal processing, 10(3), 1995, pp. 237-260
FAULT-TOLERANT DESIGN METHODOLOGY FOR SYSTOLIC ARRAY ARCHITECTURES
Authors: ESONU MO ALKHALILI AJ HARIRI S ALKHALILI D
Citation: Mo. Esonu et al., FAULT-TOLERANT DESIGN METHODOLOGY FOR SYSTOLIC ARRAY ARCHITECTURES, IEE proceedings. Computers and digital techniques, 141(1), 1994, pp. 17-28
Risultati: 1-3 |