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Results: 1-9 |
Results: 9
Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects
Authors: Jin, WJ Eo, Y Eisenstadt, WR Shim, J
Citation: Wj. Jin et al., Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects, IEEE VLSI, 9(3), 2001, pp. 450-460
S-parameter-measurement-based high-speed signal transient characterizationof VLSI interconnects on SiO2-Si substrate
Authors: Eo, Y Eisenstadt, WR Shim, J
Citation: Y. Eo et al., S-parameter-measurement-based high-speed signal transient characterizationof VLSI interconnects on SiO2-Si substrate, IEEE T AD P, 23(3), 2000, pp. 470-479
New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design
Authors: Eo, Y Eisenstadt, WR Jeong, JY Kwon, OK
Citation: Y. Eo et al., New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design, IEEE T AD P, 23(2), 2000, pp. 303-312
Experimental characterization and modeling of transmission line effects for high-speed VLSI circuit interconnects
Authors: Jin, W Yoon, S Eo, Y Kim, J
Citation: W. Jin et al., Experimental characterization and modeling of transmission line effects for high-speed VLSI circuit interconnects, IEICE TR EL, E83C(5), 2000, pp. 728-735
Reference SAW oscillator on quartz-on-silicon (QoS) wafer for polylithic integration of true single chip radio
Authors: Eo, Y Hyun, S Lee, K Oh, G Lee, JW
Citation: Y. Eo et al., Reference SAW oscillator on quartz-on-silicon (QoS) wafer for polylithic integration of true single chip radio, IEEE ELEC D, 21(8), 2000, pp. 393-395
A new on-chip interconnect crosstalk model and experimental verification fur CMOS VLSI circuit design
Authors: Eo, Y Eisenstadt, WR Jeong, JY Kwon, OH
Citation: Y. Eo et al., A new on-chip interconnect crosstalk model and experimental verification fur CMOS VLSI circuit design, IEEE DEVICE, 47(1), 2000, pp. 129-140
Non-uniform multi-layer IC interconnect transmission line characterizationfor fast signal transient simulation of high-speed/high-density VLSI circuits
Authors: Jin, WJ Yoo, H Eo, Y
Citation: Wj. Jin et al., Non-uniform multi-layer IC interconnect transmission line characterizationfor fast signal transient simulation of high-speed/high-density VLSI circuits, IEICE TR EL, E82C(6), 1999, pp. 955-966
Simulator for interconnects and general multiline analysis (SIGMA): Simulation algorithm of lossy multiple transmission lines
Authors: Kim, YJ Park, YJ Eo, Y Kwon, OK Lee, C
Citation: Yj. Kim et al., Simulator for interconnects and general multiline analysis (SIGMA): Simulation algorithm of lossy multiple transmission lines, J KOR PHYS, 33, 1998, pp. S129-S134
Utilization of photon emission microscopy in determining drain junction property of submicron NMOSFETs
Authors: Lee, SG Jeong, JY Hwang, JM Eo, Y Kwon, OK
Citation: Sg. Lee et al., Utilization of photon emission microscopy in determining drain junction property of submicron NMOSFETs, J KOR PHYS, 33, 1998, pp. S220-S223
Risultati: 1-9 |