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Results:
1-7
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Results: 7
Authors:
BAHAR RI
CHO H
HACHTEL GD
MACII E
SOMENZI F
Citation: Ri. Bahar et al., SYMBOLIC TIMING ANALYSIS AND RESYNTHESIS FOR LOW-POWER OF COMBINATIONAL-CIRCUITS CONTAINING FALSE PATHS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(10), 1997, pp. 1101-1115
Authors:
CHO H
HACHTEL GD
MACII E
PONCINO M
SOMENZI F
Citation: H. Cho et al., AUTOMATIC STATE-SPACE DECOMPOSITION FOR APPROXIMATE FSM TRAVERSAL BASED ON CIRCUIT ANALYSIS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(12), 1996, pp. 1451-1464
Authors:
CHO H
HACHTEL GD
MACII E
PLESSIER B
SOMENZI F
Citation: H. Cho et al., ALGORITHMS FOR APPROXIMATE FSM TRAVERSAL BASED ON STATE-SPACE DECOMPOSITION, IEEE transactions on computer-aided design of integrated circuits and systems, 15(12), 1996, pp. 1465-1478
Authors:
HACHTEL GD
MACII E
PARDO A
SOMENZI F
Citation: Gd. Hachtel et al., MARKOVIAN ANALYSIS OF LARGE FINITE-STATE MACHINES, IEEE transactions on computer-aided design of integrated circuits and systems, 15(12), 1996, pp. 1479-1493
Authors:
PIXLEY C
JEONG SW
HACHTEL GD
Citation: C. Pixley et al., EXACT CALCULATION OF SYNCHRONIZING SEQUENCES BASED ON BINARY DECISIONDIAGRAMS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(8), 1994, pp. 1024-1034
Authors:
RHO JK
HACHTEL GD
SOMENZI F
JACOBY RM
Citation: Jk. Rho et al., EXACT AND HEURISTIC ALGORITHMS FOR THE MINIMIZATION OF INCOMPLETELY SPECIFIED STATE MACHINES, IEEE transactions on computer-aided design of integrated circuits and systems, 13(2), 1994, pp. 167-177
Authors:
CHO H
HACHTEL GD
SOMENZI F
Citation: H. Cho et al., REDUNDANCY IDENTIFICATION REMOVAL AND TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING IMPLICIT STATE ENUMERATION, IEEE transactions on computer-aided design of integrated circuits and systems, 12(7), 1993, pp. 935-945
Risultati:
1-7
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