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Results: 1-3 |
Results: 3

Authors: Enomoto, T Hirobe, A Fujii, M Yoshida, N Asai, S
Citation: T. Enomoto et al., Low-voltage, low-power, high-speed 0.25-mu m GaAsHEMT delay flip-flops, IEICE TR EL, E83C(11), 2000, pp. 1774-1785

Authors: Isa, S Takai, Y Fujita, M Nagata, K Nakazawa, S Hirobe, A
Citation: S. Isa et al., A 1Gbit DDR-SDRAM, NEC RES DEV, 41(1), 2000, pp. 87-92

Authors: Takai, Y Fujita, M Nagata, K Isa, S Nakazawa, S Hirobe, A Ohkubo, H Sakao, M Horiba, S Fukase, T Takaishi, Y Matsuo, M Komuro, M Uchida, T Sakoh, T Saino, K Uchiyama, S Takada, Y Sekine, J Nakanishi, N Oikawa, T Igeta, M Tanabe, H Miyamoto, H Hashimoto, T Yamaguchi, H Koyama, K Kobayashi, Y Okuda, T
Citation: Y. Takai et al., A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay andan interbank shared redundancy scheme, IEEE J SOLI, 35(2), 2000, pp. 149-162
Risultati: 1-3 |