Authors:
Moller, L
Thiede, A
Chandrasekhar, S
Benz, W
Lang, M
Jakobus, T
Schlechtweg, M
Citation: L. Moller et al., ISI mitigation using decision feedback loop demonstrated with PMD distorted 10Gbit/s signals, ELECTR LETT, 35(24), 1999, pp. 2092-2093
Authors:
Wang, ZG
Thiede, A
Schlechtweg, M
Lienhart, H
Hulsmann, A
Raynor, B
Schneider, J
Jakobus, T
Citation: Zg. Wang et al., 40Gbit/s/GHz clock recovery and frequency multiplying AlGaAs/GaAs-HEMT-IC using injection-synchronised narrowband ring-VCOs and auxiliary PLLs, ELECTR LETT, 35(14), 1999, pp. 1151-1152