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Results: 1
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface
Authors:
Kim, C Kyung, KH Jeong, WP Kim, JS Moon, BS Chai, JW Yim, SM Choi, JH Han, KH Park, CJ Hwang, HS Choi, H Cho, SB Portmann, CL Cho, SI
Citation:
C. Kim et al., A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface, IEEE J SOLI, 34(5), 1999, pp. 645-652
Risultati:
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