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Results:
1-5
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Results: 5
ADir(p)NB: A cost-effective way to implement full map directory-based cache coherence protocols
Authors:
Li, T John, LK
Citation:
T. Li et Lk. John, ADir(p)NB: A cost-effective way to implement full map directory-based cache coherence protocols, IEEE COMPUT, 50(9), 2001, pp. 921-934
Java runtime systems: Characterization and architectural implications
Authors:
Radhakrishnan, R Vijaykrishnan, N John, LK Sivasubramaniam, A Rubio, J Sabarinathan, J
Citation:
R. Radhakrishnan et al., Java runtime systems: Characterization and architectural implications, IEEE COMPUT, 50(2), 2001, pp. 131-146
Data placement schemes to reduce conflicts in interleaved memories
Authors:
John, LK
Citation:
Lk. John, Data placement schemes to reduce conflicts in interleaved memories, COMPUTER J, 43(2), 2000, pp. 138-151
Memory chips with adjustable configurations
Authors:
John, LK
Citation:
Lk. John, Memory chips with adjustable configurations, VLSI DESIGN, 10(2), 1999, pp. 203-215
Annex cache: a cache assist to implement selective caching
Authors:
John, LK Li, T Subramanian, A
Citation:
Lk. John et al., Annex cache: a cache assist to implement selective caching, MICROPR MIC, 23(8-9), 1999, pp. 537-551
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