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Results: 1-7 |
Results: 7
DUAL-POLYCIDE GATE TECHNOLOGY USING REGROWTH AMORPHOUS-SI TO SUPPRESSLATERAL DOPANT DIFFUSION
Authors: KOIKE H UNNO Y MATSUOKA F KAKUMU M
Citation: H. Koike et al., DUAL-POLYCIDE GATE TECHNOLOGY USING REGROWTH AMORPHOUS-SI TO SUPPRESSLATERAL DOPANT DIFFUSION, I.E.E.E. transactions on electron devices, 44(9), 1997, pp. 1460-1466
DESIGN METHODOLOGY OF DEEP-SUBMICRON CMOS DEVICES FOR 1V OPERATION
Authors: OYAMATSU H KINUGAWA M KAKUMU M
Citation: H. Oyamatsu et al., DESIGN METHODOLOGY OF DEEP-SUBMICRON CMOS DEVICES FOR 1V OPERATION, IEICE transactions on electronics, E79C(12), 1996, pp. 1720-1725
SIMPLE AND QUICK TURNAROUND TIME FABRICATION PROCESS FOR DEEP-SUBMICROMETER CMOS GENERATION
Authors: KOIKE H MATSUOKA F OHTSUKA H KAKUMU M
Citation: H. Koike et al., SIMPLE AND QUICK TURNAROUND TIME FABRICATION PROCESS FOR DEEP-SUBMICROMETER CMOS GENERATION, IEEE transactions on semiconductor manufacturing, 9(4), 1996, pp. 489-494
LOW-RESISTIVITY POLY-METAL GATE ELECTRODE DURABLE FOR HIGH-TEMPERATURE PROCESSING
Authors: AKASAKA Y SUEHIRO S NAKAJIMA K NAKASUGI T MIYANO K KASAI K OYAMATSU H KINUGAWA M TAKAGI MT AGAWA K MATSUOKA F KAKUMU M SUGURO K
Citation: Y. Akasaka et al., LOW-RESISTIVITY POLY-METAL GATE ELECTRODE DURABLE FOR HIGH-TEMPERATURE PROCESSING, I.E.E.E. transactions on electron devices, 43(11), 1996, pp. 1864-1869
A 0.9-V, 150-MHZ, 10-MW, 4 MM(2), 2-D DISCRETE COSINE TRANSFORM CORE PROCESSOR WITH VARIABLE THRESHOLD-VOLTAGE (VT) SCHEME
Authors: KURODA T FUJITA T MITA S NAGAMATSU T YOSHIOKA S SUZUKI K SANO F NORISHIMA M MUROTA M KAKO M KINUGAWA M KAKUMU M SAKURAI T
Citation: T. Kuroda et al., A 0.9-V, 150-MHZ, 10-MW, 4 MM(2), 2-D DISCRETE COSINE TRANSFORM CORE PROCESSOR WITH VARIABLE THRESHOLD-VOLTAGE (VT) SCHEME, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1770-1779
HIGH-DENSITY FULL-CMOS SRAM CELL TECHNOLOGY WITH A DEEP-SUBMICRON SPACING BETWEEN NMOS AND PMOSFET
Authors: MATSUOKA F ISHIMARU K GOJOHBORI H KOIKE H UNNO Y SAI M KONDO T ICHIKAWA R KAKUMU M
Citation: F. Matsuoka et al., HIGH-DENSITY FULL-CMOS SRAM CELL TECHNOLOGY WITH A DEEP-SUBMICRON SPACING BETWEEN NMOS AND PMOSFET, IEICE transactions on electronics, E77C(8), 1994, pp. 1385-1394
PROCESS AND DEVICE TECHNOLOGIES OF CMOS DEVICES FOR LOW-VOLTAGE OPERATION
Authors: KAKUMU M
Citation: M. Kakumu, PROCESS AND DEVICE TECHNOLOGIES OF CMOS DEVICES FOR LOW-VOLTAGE OPERATION, IEICE transactions on electronics, E76C(5), 1993, pp. 672-680
Risultati: 1-7 |