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Authors: IWABUCHI M USAMI M KASHIYAMA M OOMORI T MURATA S HIRAMOTO T HASHIMOTO T NAKAJIMA Y

Citation: M. Iwabuchi et al., A 1.5-NS CYCLE-TIME 18-KB PSEUDO-DUAL-PORT RAM WITH 9K LOGIC GATES, IEICE transactions on electronics, E77C(5), 1994, pp. 749-755

Authors: IWABUCHI M USAMI M KASHIYAMA M OOMORI T MURATA S HIRAMOTO T HASHIMOTO T NAKAJIMA Y

Citation: M. Iwabuchi et al., A 1.5-NS CYCLE-TIME 18-KB PSEUDO-DUAL-PORT RAM WITH 9K LOGIC GATES, IEEE journal of solid-state circuits, 29(4), 1994, pp. 419-425