Authors: Kubosawa, H Higaki, N Ando, S Takahashi, H Asada, Y Anbutsu, H Sato, T Sakate, M Suga, A Kimura, M Miyake, H Okano, H Asato, A Kimura, Y Nakayama, H Kimoto, M Hirochi, K Saito, H Kaido, N Nakagawa, Y Shimada, T

Citation: H. Kubosawa et al., A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism, IEEE J SOLI, 34(11), 1999, pp. 1619-1626