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Citation: S. Maeda et al., Feasibility of 0.18 mu m SOI CMOS technology using hybrid trench isolationwith high resistivity substrate for embedded RF/analog applications, IEEE DEVICE, 48(9), 2001, pp. 2065-2073

Authors: Yamamoto, K Heima, T Furukawa, A Ono, M Hashizume, Y Komurasaki, H Maeda, S Sato, H Kato, N

Citation: K. Yamamoto et al., A 2.4-GHz-Band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end witha low insertion loss switch, IEEE J SOLI, 36(8), 2001, pp. 1186-1197

Authors: Komurasaki, H Sato, H Yamamoto, K Ueda, K Maeda, S Yamaguchi, Y Sasaki, N Miki, T Horiba, Y

Citation: H. Komurasaki et al., A sub 1-V L-band low noise amplifier in SOICMOS, IEICE T FUN, E83A(2), 2000, pp. 220-227