Citation: Jh. Lou et Jb. Kuo, A 1.5-V BOOTSTRAPPED PASS-TRANSISTOR-BASED MANCHESTER CARRY CHAIN CIRCUIT SUITABLE FOR IMPLEMENTING LOW-VOLTAGE CARRY LOOK-AHEAD ADDERS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 45(11), 1998, pp. 1191-1194
Authors:
JAGER F
LOU JH
NAKANISHI K
UJJ L
ATKINSON GH
Citation: F. Jager et al., VIBRATIONAL SPECTROSCOPY OF A PICOSECOND, STRUCTURALLY-RESTRICTED INTERMEDIATE CONTAINING A 7-MEMBERED RING IN THE ROOM-TEMPERATURE PHOTOREACTION OF AN ARTIFICIAL RHODOPSIN, Journal of the American Chemical Society, 120(15), 1998, pp. 3739-3747
Citation: Pf. Lin et al., A CMOS QUADRATURE MODULATOR FOR WIRELESS COMMUNICATION IC, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 44(6), 1997, pp. 559-561
Authors:
TAN Q
LOU JH
BORHAN B
KARNAUKHOVA E
BEROVA N
NAKANISHI K
Citation: Q. Tan et al., ABSOLUTE SENSE OF TWIST OF THE C-12-C-13 BOND OF THE RETINAL CHROMOPHORE IN BOVINE RHODOPSIN BASED ON EXCITON-COUPLED CD SPECTRA OF 11,12-DIHYDRORETINAL ANALOGS, Angewandte Chemie, International Edition in English, 36(19), 1997, pp. 2089-2093
Authors:
HAN M
LOU JH
NAKANISHI K
SAKMAR TP
SMITH SO
Citation: M. Han et al., PARTIAL AGONIST ACTIVITY OF 11-CIS-RETINAL IN RHODOPSIN MUTANTS, The Journal of biological chemistry, 272(37), 1997, pp. 23081-23085
Citation: Jh. Lou et Jb. Kuo, A 1.5-V FULL-SWING BOOTSTRAPPED CMOS LARGE CAPACITIVE-LOAD DRIVER CIRCUIT SUITABLE FOR LOW-VOLTAGE CMOS VLSI, IEEE journal of solid-state circuits, 32(1), 1997, pp. 119-121
Citation: Cc. Yeh et al., 1.5 V CMOS FULL-SWING ENERGY-EFFICIENT LOGIC (EEL) CIRCUIT SUITABLE FOR LOW-VOLTAGE AND LOW-POWER VLSI APPLICATIONS, Electronics Letters, 33(16), 1997, pp. 1375-1376
Authors:
SHEN SY
LOU JH
CHENG JX
HONG KL
ZHU QG
ZHOU XY
Citation: Sy. Shen et al., STUDIES ON THE FREE-VOLUME CHANGE IN ANNEALED ULTRA-HIGH-MOLECULAR-WEIGHT POLYETHYLENE BY THE POSITRON-ANNIHILATION TECHNIQUE, Physica status solidi. a, Applied research, 147(2), 1995, pp. 447-452
Citation: Jb. Kuo et al., A BICMOS DYNAMIC MULTIPLIER USING WALLACE TREE REDUCTION ARCHITECTUREAND 1.5-V FULL-SWING BICMOS DYNAMIC LOGIC-CIRCUIT, IEEE journal of solid-state circuits, 30(8), 1995, pp. 950-954
Citation: Jb. Kuo et al., A 1.5-V BICMOS DYNAMIC LOGIC-CIRCUIT USING A BIPMOS PULL-DOWN STRUCTURE FOR VLSI IMPLEMENTATION OF FULL ADDERS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 41(4), 1994, pp. 329-332