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Results: 1-3 |
Results: 3
Cleaning status on low-k dielectric in advanced VLSI interconnect: Characterisation and principal issues
Authors: Louis, D Beverina, A Arvet, C Lajoinie, E Peyne, C Holmes, D Maloney, D
Citation: D. Louis et al., Cleaning status on low-k dielectric in advanced VLSI interconnect: Characterisation and principal issues, MICROEL ENG, 57-8, 2001, pp. 621-627
Resist removal process in dual damascene structure integrating Cu and SiLK(R) for 0.18 mu m technology.
Authors: Louis, D Arvet, C Lajoinie, E Peyne, C Lee, S Berry, I Han, Q
Citation: D. Louis et al., Resist removal process in dual damascene structure integrating Cu and SiLK(R) for 0.18 mu m technology., MICROEL ENG, 53(1-4), 2000, pp. 381-384
Improved post etch cleaning for low-k and copper integration for 0.18 mu mtechnology
Authors: Louis, D Peyne, C Lajoinie, E Vallesi, B Holmes, D Maloney, D Lee, S
Citation: D. Louis et al., Improved post etch cleaning for low-k and copper integration for 0.18 mu mtechnology, MICROEL ENG, 46(1-4), 1999, pp. 307-310
Risultati: 1-3 |