Authors:
BAFLEUR M
VIDAL MP
GIVELIN JBP
MACARY V
SARRABAYROUSE G
Citation: M. Bafleur et al., COST-EFFECTIVE SMART POWER CMOS DMOS TECHNOLOGY - DESIGN METHODOLOGY FOR LATCH-UP IMMUNITY/, Analog integrated circuits and signal processing, 8(3), 1995, pp. 219-231
Authors:
GIVELIN MBP
VIDAL MP
BUXO J
MACARY V
SISKOS S
LAOPOULOS T
Citation: Mbp. Givelin et al., COST-EFFECTIVE SMART POWER CMOS DMOS TECHNOLOGY - DESIGN OF MAIN DRIVING AND PROTECTION FUNCTIONS/, Analog integrated circuits and signal processing, 8(3), 1995, pp. 233-246
Authors:
BAFLEUR M
BUXO J
VIDAL MP
GIVELIN P
MACARY V
SARRABAYROUSE G
Citation: M. Bafleur et al., APPLICATION OF A FLOATING WELL CONCEPT TO A LATCH-UP-FREE, LOW-COST, SMART POWER HIGH-SIDE SWITCH TECHNOLOGY, I.E.E.E. transactions on electron devices, 40(7), 1993, pp. 1340-1342