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Results: 3

Authors: BASU A BANERJI DK BASU A WILSON TC MAJITHIA JC
Citation: A. Basu et al., A MODIFIED APPROACH TO TEST PLAN GENERATION FOR COMBINATIONAL LOGIC BLOCKS, VLSI design, 4(3), 1996, pp. 243-256

Authors: JIANG HH MAJITHIA JC
Citation: Hh. Jiang et Jc. Majithia, SUGGESTION FOR A NEW REPRESENTATION FOR BINARY FUNCTION, I.E.E.E. transactions on computers, 45(12), 1996, pp. 1445-1449

Authors: JIANG H MAJITHIA JC
Citation: H. Jiang et Jc. Majithia, CHIP LEVEL FAULT LOCATION USING X-ALGORITHM, IEE proceedings. Computers and digital techniques, 141(5), 1994, pp. 259-264
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