CHIP LEVEL FAULT LOCATION USING X-ALGORITHM

Citation
H. Jiang et Jc. Majithia, CHIP LEVEL FAULT LOCATION USING X-ALGORITHM, IEE proceedings. Computers and digital techniques, 141(5), 1994, pp. 259-264
Citations number
6
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture","Computer Science Theory & Methods
ISSN journal
13502387
Volume
141
Issue
5
Year of publication
1994
Pages
259 - 264
Database
ISI
SICI code
1350-2387(1994)141:5<259:CLFLUX>2.0.ZU;2-6
Abstract
In board level testing the faults are usually isolated to a field repl acement unit (FRU) rather than to a single chip. In this paper a new a lgorithm, called the X-algorithm, is presented to locate a faulty chip in an FRU. The location patterns (LPs) which contain only one symbol X/(X) over bar are introduced. The trajectory of the X/(X) over bar pr opagation sensitises the faults in the FRU. Based on the test results the LPs can be generated easily. In the X-algorithm the X/(X) over bar propagation trajectory is analysed so that the faulty chip can be loc ated automatically. Preliminary results show that the algorithm is qui te effective, and it may not be necessary to exhaustively simulate wit h the LPs.