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A LOW-POWER DSP CORE ARCHITECTURE FOR LOW BITRATE SPEECH CODEC
Authors:
OKUHATA H MIKI MH ONOYE T SHIRAKAWA I
Citation:
H. Okuhata et al., A LOW-POWER DSP CORE ARCHITECTURE FOR LOW BITRATE SPEECH CODEC, IEICE transactions on fundamentals of electronics, communications and computer science, E81A(8), 1998, pp. 1616-1621
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