Citation: A. Motohara et al., A PARTIAL SCAN DESIGN APPROACH BASED ON REGISTER-TRANSFER LEVEL TESTABILITY ANALYSIS, IEICE transactions on information and systems, E79D(10), 1996, pp. 1436-1442
Authors:
CHOI H
MAEDA H
KOHARA T
ISHIURA N
SHIRAKAWA I
MOTOHARA A
Citation: H. Choi et al., TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING PARTITIONED IMAGE COMPUTATION, IEICE transactions on fundamentals of electronics, communications and computer science, E76A(10), 1993, pp. 1770-1774