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Results: 2
High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters
Authors: Mohanty, BK Meher, PK
Citation: Bk. Mohanty et Pk. Meher, High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters, IEE P-COM D, 146(2), 1999, pp. 91-99
High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier
Authors: Nayak, SS Meher, PK
Citation: Ss. Nayak et Pk. Meher, High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier, IEEE CIR-II, 46(5), 1999, pp. 655-658
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