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Results:
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Results: 2
INTERCONNECT AND CIRCUIT MODELING TECHNIQUES FOR FULL-CHIP POWER-SUPPLY NOISE-ANALYSIS
Authors:
CHEN HH NEELY JS
Citation:
Hh. Chen et Js. Neely, INTERCONNECT AND CIRCUIT MODELING TECHNIQUES FOR FULL-CHIP POWER-SUPPLY NOISE-ANALYSIS, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 21(3), 1998, pp. 209-215
A ROOM-TEMPERATURE 0.1 MU-M CMOS ON SOI
Authors:
SHAHIDI GG ANDERSON CA CHAPPELL BA CHAPPELL TI COMFORT JH DAVARI B DENNARD RH FRANCH RL MCFARLAND PA NEELY JS NING TH POLCARI MR WARNOCK JD
Citation:
Gg. Shahidi et al., A ROOM-TEMPERATURE 0.1 MU-M CMOS ON SOI, I.E.E.E. transactions on electron devices, 41(12), 1994, pp. 2405-2412
Risultati:
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