A ROOM-TEMPERATURE 0.1 MU-M CMOS ON SOI

An advanced 0.1 mu m CMOS technology on SOI is presented, In order to minimize short channel effects, relatively thick nondepleted (0.15 mu m) SOI film, highly nonuniform channel doping and source-drain extensi on-halo were used. Excellent short channel effects (SCE) down to chann el lengths below 0.1 mu m were obtained. It is shown that undepleted S OI results in better short channel effect when compared to ultrathin d epleted SOI, Devices with little short channel effect all the way to b elow 500 Angstrom effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effe ct inherent in the floating body, These devices were applied to a vari ety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI = FO = 3) was 64 ps, and loaded NAND (FI = FO = 3, C-L = 0.3 pF) delay was 130 ps at supply of 1.8 V, This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained.