Authors:
VILLA T
SALDANHA A
BRAYTON RK
SANGIOVANNIVINCENTELLI AL
Citation: T. Villa et al., SYMBOLIC 2-LEVEL MINIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(7), 1997, pp. 692-708
Authors:
LAM WK
SALDANHA A
BRAYTON RK
SANGIOVANNIVINCENTELLI AL
Citation: Wk. Lam et al., DELAY-FAULT COVERAGE, TEST SET SIZE, AND PERFORMANCE TRADE-OFFS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(1), 1995, pp. 32-44
Authors:
SALDANHA A
BRAYTON RK
SANGIOVANNIVINCENTELLI AL
Citation: A. Saldanha et al., CIRCUIT STRUCTURE RELATIONS TO REDUNDANCY AND DELAY, IEEE transactions on computer-aided design of integrated circuits and systems, 13(7), 1994, pp. 875-883
Authors:
SALDANHA A
VILLA T
BRAYTON RK
SANGIOVANNIVINCENTELLI AL
Citation: A. Saldanha et al., SATISFACTION OF INPUT AND OUTPUT ENCODING CONSTRAINTS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(5), 1994, pp. 589-602