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Results: 5

Authors: HUR Y SZYGENDA SA
Citation: Y. Hur et Sa. Szygenda, DESIGN ERROR SIMULATION-BASED ON ERROR MODELING AND SAMPLING TECHNIQUES, Mathematics and computers in simulation, 46(1), 1998, pp. 35-46

Authors: FEHR ES SZYGENDA SA OTT GE
Citation: Es. Fehr et al., AN INTEGRATED HARDWARE ARRAY FOR VERY HIGH-SPEED LOGIC SIMULATION, VLSI design, 4(2), 1996, pp. 107-118

Authors: KANG S HUR Y SZYGENDA SA
Citation: S. Kang et al., A HARDWARE ACCELERATOR FOR FAULT SIMULATION UTILIZING A RECONFIGURABLE ARRAY ARCHITECTURE, VLSI design, 4(2), 1996, pp. 119-133

Authors: KANG SH SZYGENDA SA
Citation: Sh. Kang et Sa. Szygenda, DESIGN VALIDATION - COMPARING THEORETICAL AND EMPIRICAL RESULTS OF DESIGN ERROR MODELING, IEEE design & test of computers, 11(1), 1994, pp. 18-26

Authors: KANG S SZYGENDA SA
Citation: S. Kang et Sa. Szygenda, AUTOMATIC SIMULATOR GENERATION SYSTEM, Simulation, 63(6), 1994, pp. 360-368
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