AN INTEGRATED HARDWARE ARRAY FOR VERY HIGH-SPEED LOGIC SIMULATION

A hardware architecture is proposed which allows direct mapping of des ign simulation topology onto an acceleration platform. In order to cla rify architectural principles, the simulation is confined to functiona l verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural inno vation reduces logic complexity and execution time of boolean evaluati on and fanout switching circuits, while large scale parallelism is int egrated at die level to reduce cost and communication delays. The resu lts of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for ha rdware gate level simulation accelerators.