Authors: Rajendran, K Samudra, G

Citation: K. Rajendran et G. Samudra, A simple modelling of device speed in double-gate SOI MOSFETs, MICROELEC J, 31(4), 2000, pp. 255-259

Authors: Samudra, G Rajendran, K

Citation: G. Samudra et K. Rajendran, Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices, INT J ELECT, 87(5), 2000, pp. 513-530

Authors: Samudra, G Rajendran, K

Citation: G. Samudra et K. Rajendran, Scaling parameter dependent drain induced barrier lowering effect in double-gate silicon-on-insulator metal-oxide-semiconductor field effect transistor, JPN J A P 2, 38(4A), 1999, pp. L349-L352