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Results:
1-4
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Results: 4
Adding reconfigurable logic to SOC designs
Authors:
Gupta, B Parviainen, JA Schaumont, P Tanurhan, Y Roy, K
Citation:
B. Gupta et al., Adding reconfigurable logic to SOC designs, IEEE DES T, 18(4), 2001, pp. 65-71
System-on-chip specification and modeling using C++: Challenges and opportunities
Authors:
Sanguinetti, J Schaumont, P Bhatt, R Liao, S Lennard, CK De Micheli, G Gajski, DD
Citation:
J. Sanguinetti et al., System-on-chip specification and modeling using C++: Challenges and opportunities, IEEE DES T, 18(3), 2001, pp. 115-123
High level analysis of clock regions in a C++ system description
Authors:
Rynders, L Schaumont, P Vernalde, S Bolsens, I
Citation:
L. Rynders et al., High level analysis of clock regions in a C++ system description, IEICE T FUN, E83A(12), 2000, pp. 2631-2632
A new algorithm for elimination of common subexpressions
Authors:
Pasko, R Schaumont, P Derudder, V Vernalde, S Durackova, D
Citation:
R. Pasko et al., A new algorithm for elimination of common subexpressions, IEEE COMP A, 18(1), 1999, pp. 58-68
Risultati:
1-4
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