Authors: Strehl, K Thiele, L Gries, M Ziegenbein, D Ernst, R Teich, J

Citation: K. Strehl et al., FunState - An internal design representation for codesign, IEEE VLSI, 9(4), 2001, pp. 524-544

Authors: Strehl, K Thiele, L

Citation: K. Strehl et L. Thiele, Interval diagrams for efficient symbolic verification of process networks, IEEE COMP A, 19(8), 2000, pp. 939-956