Authors: MAEGAWA S IPPOSHI T MAEDA S NISHIMURA H TANINA O KURIYAMA H INOUE Y NISHIMURA T TSUBOUCHI N

Citation: S. Maegawa et al., A 0.4 MU-M GATE-ALL-AROUND TFT (GAT) USING A DUMMY NITRIDE PATTERN FOR HIGH-DENSITY MEMORIES, JPN J A P 1, 34(2B), 1995, pp. 895-899

Authors: MAEGAWA S IPPOSHI T MAEDA S NISHIMURA H ICHIKI T ASHIDA M TANINA O INOUE Y NISHIMURA T TSUBOUCHI N

Citation: S. Maegawa et al., PERFORMANCE AND RELIABILITY IMPROVEMENTS IN POLY-SI TFTS BY FLUORINE IMPLANTATION INTO GATE POLY-SI, I.E.E.E. transactions on electron devices, 42(6), 1995, pp. 1106-1112

Authors: MAEDA S MAEGAWA S IPPOSHI T NISHIMURA H KURIYAMA H TANINA O INOUE Y NISHIMURA T TSUBOUCHI N

Citation: S. Maeda et al., IMPACT OF A VERTICAL PHI-SHAPE TRANSISTOR (V-PHI-T) CELL FOR 1 GBIT DRAM AND BEYOND, I.E.E.E. transactions on electron devices, 42(12), 1995, pp. 2117-2124