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Results: 1-2 |
Results: 2
A 3 V low power 156/622/1244 Mbps CMOS parallel clock and data recovery circuit for optical communications
Authors: Seo, HM Woo, CG Oh, SW Jung, SW Choi, P
Citation: Hm. Seo et al., A 3 V low power 156/622/1244 Mbps CMOS parallel clock and data recovery circuit for optical communications, IEICE T FUN, E83A(8), 2000, pp. 1720-1727
Design and implementation of a fourth-order quadrature band-pass delta-sigma modulator for low-IF receivers
Authors: Jung, SW Woo, CG Oh, SW Seo, HM Choi, P
Citation: Sw. Jung et al., Design and implementation of a fourth-order quadrature band-pass delta-sigma modulator for low-IF receivers, IEICE T FUN, E83A(12), 2000, pp. 2649-2656
Risultati: 1-2 |