A CMOS IMAGER HYBRIDIZED TO AN AVALANCHE MULTIPLIED FILM

Authors
TAKIGUCHI Y MARUYAMA H KOSUGI M ANDOH F KATO T TANIOKA K YAMAZAKI J TSUJI K KAWAMURA T
Citation
Y. Takiguchi et al., A CMOS IMAGER HYBRIDIZED TO AN AVALANCHE MULTIPLIED FILM, I.E.E.E. transactions on electron devices, 44(10), 1997, pp. 1783-1788
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic","Physics, Applied
Journal title
I.E.E.E. transactions on electron devices → ACNP
ISSN journal
00189383
Volume
44
Issue
10
Year of publication
1997
Pages
1783 - 1788
Database
ISI
SICI code
0018-9383(1997)44:10<1783:ACIHTA>2.0.ZU;2-S
Abstract
A highly sensitive solid-state imager has been made by connecting an a valanche multiplier film to a MOS readout circuit through microbump el ectrodes. Optimization of the vapor-deposition conditions for the indi um bump material made it possible for microbumps 5 mu m in diameter an d 5 mu m in height to be formed into a 2/3-in matrix array of 380 000 pixels. A prototype imager was constructed with a 0.5-mu m thick avala nche photoconductive film. Clear avalanche multiplication of about ten times was observed at an applied voltage of 75 V. The imager had a go od resolution and no recognizable afterimages.