PREDICTING CMOS SPEED WITH GATE OXIDE AND VOLTAGE SCALING AND INTERCONNECT LOADING EFFECTS

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physica l gate oxide thicknesses have been studied at supply voltages of 1.5-3 .3 V. I-dsat can be accurately predicted from a universal mobility mod el and a current model considering velocity saturation and parasitic s eries resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different i nterconnect loading are highlighted.