GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS CONDITIONS

Authors
VERHAEGE K RUSS C LUCHIES JM GROESENEKEN G KUPER FG
Citation
K. Verhaege et al., GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS CONDITIONS, I.E.E.E. transactions on electron devices, 44(11), 1997, pp. 1972-1980
Citations number
32
Categorie Soggetti
Engineering, Eletrical & Electronic","Physics, Applied
Journal title
I.E.E.E. transactions on electron devices → ACNP
ISSN journal
00189383
Volume
44
Issue
11
Year of publication
1997
Pages
1972 - 1980
Database
ISI
SICI code
0018-9383(1997)44:11<1972:GNTBUC>2.0.ZU;2-P
Abstract
This paper contains a systematic study into the effects of design and process variations on the behavior of the grounded-gate nMOS transisto r under CDM ESD stress conditions. The correlation of both electrical behavior and physical failure is evaluated for socketed CDM, nonsocket ed CDM, and HEM ESD stress models. It is shown that a new compact tran sistor model, concerning its application for the simulation of CDM beh avior, is employed in electro-thermal simulation to explain the experi mental results.