LIFETIME PREDICTION FOR PMOS, AND NMOS DEVICES BASED ON A DEGRADATIONMODEL FOR GATE-BIAS-STRESS

The degradation behaviour of PMOS and NMOS devices after Gate-Bias-str ess (GB-stress) was investigated. The observed saturation current decr ease of p-channel devices after GB-stress is due to field-induced gene ration of interface states. The decrease of saturation current of n-ch annel devices after GB-stress can be interpreted by trapped electrons, which are tunneling from the substrate into the gate oxide. Based on the experimental lifetime results at stress conditions extrapolation m odels were formulated which allow the determination of lifetime after GB-stress both for n- and p-channel devices at real operation conditio ns. (C) 1997 Elsevier Science Ltd.