COMPARISON OF DIFFERENT ON-CHIP ESD PROTECTION STRUCTURES IN A 0.35 MU-M CMOS TECHNOLOGY

In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this p aper is to demonstrate that a very good ESD protection level can be ac hieved provided we can insure a uniform triggering of multifinger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (HBM) a nd Charged Device Model (CDM) test results, as well as Transmission Li ne Measurement (TLM) and light emission results support this finding. (C) 1997 Elsevier Science Ltd.