EFFECTS OF ESD PROTECTIONS ON LATCH-UP SENSITIVITY OF CMOS 4-STRIPE STRUCTURES

Authors
PAVAN P PELLESI A MENEGHESSO G ZANONI E
Citation
P. Pavan et al., EFFECTS OF ESD PROTECTIONS ON LATCH-UP SENSITIVITY OF CMOS 4-STRIPE STRUCTURES, Microelectronics and reliability, 37(10-11), 1997, pp. 1561-1564
Citations number
2
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Microelectronics and reliability → ACNP
ISSN journal
00262714
Volume
37
Issue
10-11
Year of publication
1997
Pages
1561 - 1564
Database
ISI
SICI code
0026-2714(1997)37:10-11<1561:EOEPOL>2.0.ZU;2-M
Abstract
In this paper, we present results on the influence of the turning on o f ESD protection devices on the latch-up sensitivity of 0.35 mu m CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence o f guard-rings greatly improves latch-up hardness. (C) 1997 Elsevier Sc ience Ltd.