A FLOATING-GATE MOS LEARNING ARRAY WITH LOCALLY COMPUTED WEIGHT UPDATES

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors, The array comprises one synapse transistor at ea ch node, and normalization circuitry at the row boundaries, The array computes the inner product of a column input vector and a stored weigh t matrix, The weights are stored as floating-gate charge; they are non volatile, but can increase when we apply a row-learn signal, The input and learn signals are digital pulses; column input pulses that are co incident with row-learn pulses cause weight increases at selected syna pses. The normalization circuitry forces row synapses to compete for f loating-gate charge, bounding the weight values, The array simultaneou sly exhibits fast computation and slow adaptation: The inner product c omputes in 10 mu s, whereas the weight normalization takes minutes to hours.