THE TRIPTYCH FPGA ARCHITECTURE

Citation
G. Borriello et al., THE TRIPTYCH FPGA ARCHITECTURE, IEEE transactions on very large scale integration (VLSI) systems, 3(4), 1995, pp. 491-501
Citations number
13
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
10638210
Volume
3
Issue
4
Year of publication
1995
Pages
491 - 501
Database
ISI
SICI code
1063-8210(1995)3:4<491:TTFA>2.0.ZU;2-6
Abstract
Field-programmable gate arrays (FPGA's) are an important implementatio n medium for digital logic, Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints, In this pape r we present Triptych, an FPGA architecture designed to achieve improv ed logic density with competitive performance, This is done by allowin g a permapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits, We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGA's, with comparable performance, We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface c ircuits.