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Results: 1-25/231
Authors:
CHANDRAKASAN A
SHA EHM
Citation: A. Chandrakasan et Ehm. Sha, SPECIAL SECTION ON LOW-POWER ELECTRONICS AND DESIGN, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 518-519
Authors:
WU Q
QIU Q
PEDRAM M
DING CS
Citation: Q. Wu et al., CYCLE-ACCURATE MACRO-MODELS FOR RT-LEVEL POWER ANALYSIS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 520-528
Authors:
WUYTACK S
DIGUET JP
CATTHOOR FVM
DEMAN HJ
Citation: S. Wuytack et al., FORMALIZED METHODOLOGY FOR DATA REUSE EXPLORATION FOR LOW-POWER HIERARCHICAL MEMORY MAPPINGS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 529-537
Authors:
PANT P
DE VK
CHATTERJEE A
Citation: P. Pant et al., SIMULTANEOUS POWER-SUPPLY, THRESHOLD VOLTAGE, AND TRANSISTOR SIZE OPTIMIZATION FOR LOW-POWER OPERATION OF CMOS CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 538-545
Authors:
MEHENDALE M
SHERLEKAR SD
VENKATESH G
Citation: M. Mehendale et al., LOW-POWER REALIZATION OF FIR FILTERS ON PROGRAMMABLE DSPS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 546-553
Authors:
BENINI L
DEMICHELI G
MACII E
PONCINO M
QUER S
Citation: L. Benini et al., POWER OPTIMIZATION OF CORE-BASED SYSTEMS BY ADDRESS BUS ENCODING, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 554-562
Authors:
SHAMS M
EBERGEN JC
ELMASRY MI
Citation: M. Shams et al., MODELING AND COMPARING CMOS IMPLEMENTATIONS OF THE C-ELEMENT, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 563-567
Authors:
MUSOLL E
LANG T
CORTADELLA J
Citation: E. Musoll et al., WORKING-ZONE ENCODING FOR REDUCING THE ENERGY IN MICROPROCESSOR ADDRESS BUSES, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 568-572
Authors:
SOMASEKHAR D
ROY K
Citation: D. Somasekhar et K. Roy, LVDCSL - A HIGH FAN-IN, HIGH-PERFORMANCE, LOW-VOLTAGE DIFFERENTIAL CURRENT SWITCH LOGIC FAMILY, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 573-577
Authors:
BOGLIOLO A
BENINI L
Citation: A. Bogliolo et L. Benini, ROBUST RTL POWER MACROMODELS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 578-581
Authors:
ITO K
LUCKE LE
PARHI KK
Citation: K. Ito et al., ILP-BASED COST-OPTIMAL DSP SYNTHESIS WITH MODULE SELECTION AND DATA FORMAT CONVERSION, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 582-594
Authors:
DENK TC
PARHI KK
Citation: Tc. Denk et Kk. Parhi, SYNTHESIS OF FOLDED PIPELINED ARCHITECTURES FOR MULTIRATE DSP ALGORITHMS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 595-607
Authors:
BHATIA S
JHA NK
Citation: S. Bhatia et Nk. Jha, INTEGRATION OF HIERARCHICAL TEST-GENERATION WITH BEHAVIORAL SYNTHESISOF CONTROLLER AND DATA-PATH CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 608-619
Authors:
SAVIR J
Citation: J. Savir, REDUNDANCY REVISITED, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 620-624
Authors:
JIANG YB
SAPATNEKAR SS
BAMJI C
KIM J
Citation: Yb. Jiang et al., INTERLEAVING BUFFER INSERTION AND TRANSISTOR SIZING INTO A SINGLE OPTIMIZATION, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 625-633
Authors:
HUANG JD
JOU JY
SHEN WZ
CHUANG HH
Citation: Jd. Huang et al., ON CIRCUIT CLUSTERING FOR AREA DELAY TRADEOFF UNDER CAPACITY AND PIN CONSTRAINTS/, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 634-642
Authors:
YUN KY
BEEREL PA
VAKILOTOJAR V
DOOPLY AE
ARCEO J
Citation: Ky. Yun et al., THE DESIGN AND VERIFICATION OF A HIGH-PERFORMANCE LOW-CONTROL-OVERHEAD ASYNCHRONOUS DIFFERENTIAL-EQUATION SOLVER, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 643-655
Authors:
SHNIDMAN NR
MANGIONESMITH WH
POTKONJAK M
Citation: Nr. Shnidman et al., ONLINE FAULT-DETECTION FOR BUS-BASED FIELD-PROGRAMMABLE GATE ARRAYS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 656-666
Authors:
TSAI HC
CHENG KTT
LIN CJM
BHAWMIK S
Citation: Hc. Tsai et al., EFFICIENT TEST-POINT SELECTION FOR SCAN-BASED BIST, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 667-676
Authors:
MIRANDA MA
CATTHOOR FVM
JANSSEN M
DEMAN HJ
Citation: Ma. Miranda et al., HIGH-LEVEL ADDRESS OPTIMIZATION AND SYNTHESIS TECHNIQUES FOR DATA-TRANSFER-INTENSIVE APPLICATIONS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 677-686
Authors:
KOBAYASHI K
KUBOTA S
ENOMOTO K
SEKI K
KAWAZOE K
SAKATA T
MATSUMOTO Y
HATTORI T
Citation: K. Kobayashi et al., LOW-POWER AND HIGH-QUALITY SIGNAL TRANSMISSION BASEBAND LSIC FOR PERSONAL COMMUNICATIONS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 687-696
Authors:
BAE J
PRASANNA VK
Citation: J. Bae et Vk. Prasanna, SYNTHESIS OF AREA-EFFICIENT AND HIGH-THROUGHPUT RATE DATA FORMAT CONVERTERS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 697-706
Authors:
WU AY
LIU KJR
Citation: Ay. Wu et Kjr. Liu, ALGORITHM-BASED LOW-POWER TRANSFORM CODING ARCHITECTURES - THE MULTIRATE APPROACH, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 707-718
Authors:
PASSOS NL
SHA EHM
Citation: Nl. Passos et Ehm. Sha, SCHEDULING OF UNIFORM MULTIDIMENSIONAL SYSTEMS UNDER RESOURCE CONSTRAINTS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 719-730
Authors:
JOHNSON D
AKELLA V
STOTT B
Citation: D. Johnson et al., MICROPIPELINED ASYNCHRONOUS DISCRETE COSINE TRANSFORM (DCT IDCT) PROCESSOR/, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 731-740