EFFICIENT TEST-POINT SELECTION FOR SCAN-BASED BIST

We propose a test point selection algorithm for scan-based built-in se lf-test (BIST), Under a pseudorandom BIST scheme, the objectives are 1 ) achieving a high random pattern fault coverage, 2) reducing the comp utational complexity, and 3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algo rithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing inform ation is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with fe edbacks so that the test point selection algorithm can be applied to p artial-scan circuits. The experimental results show the proposed algor ithm achieves higher fault coverages than previous approaches with a s ignificant reduction of computational complexity. By taking timing inf ormation into consideration, the performance degradation can be minimi zed with possibly more test points.