SYNTHESIS OF AREA-EFFICIENT AND HIGH-THROUGHPUT RATE DATA FORMAT CONVERTERS

This paper proposes two design methodologies for synthesis of area-eff icient data format converters (DFC's) with high throughput rate. DFC's are grouped into various classes according to the specification of de sign parameters. The first design methodology is suitable for design o f many representative classes of DFC's. The designs using this methodo logy are based on a two-dimensional (2-D) architecture. They have maxi mum throughput rate and are area-efficient. Various design examples ar e shown to demonstrate improved performance, flexibility and usefulnes s of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology e mploys an architecture using dual buffers. The simple and regular arch itecture using dual buffers leads to area-efficient DFC's. The design procedure using this methodology is simple and can reduce the design e ffort in many applications.