SIMULTANEOUS POWER-SUPPLY, THRESHOLD VOLTAGE, AND TRANSISTOR SIZE OPTIMIZATION FOR LOW-POWER OPERATION OF CMOS CIRCUITS

This paper demonstrates a new approach for minimizing the total of the static and the dynamic-power dissipation components in a complementar y metal-oxide-semiconductor (CMOS) logic network required to operate a t a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of su pply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient h euristic is developed that delivers over an order of magnitude savings in power over conventional optimization method.