POWER OPTIMIZATION OF CORE-BASED SYSTEMS BY ADDRESS BUS ENCODING

This paper presents a solution to the problem of reducing the power di ssipated by a digital system containing an intellectual proprietary co re processor which repeatedly executes a special-purpose program. The proposed method relies on a novel, application-dependent low-power add ress bus encoding scheme. The analysis of the execution traces of a gi ven program allows an accurate computation of the correlations that ma y exist between blocks of bits in consecutive patterns; this informati on can be successfully exploited to determine an encoding which sensib ly reduces the bus transition activity, Experimental results, obtained on a set of special-purpose applications, are very satisfactory; redu ctions of the bus activity up to 64.8% (41.8% on average) have been ac hieved over the original address streams. In addition, data concerning the quality and the performance of the automatically synthesized enco ding/decoding circuits, as well as the results obtained for a realisti c core-based design, indicate the practical usefulness of the proposed power optimization strategy.