A COMPUTATIONAL MODEL FOR STATIC DATA-FLOW MACHINES

Computer architects have been constantly looking for new approaches to design high-performance machines. Data flow and VLSI offer two mutual ly supportive approaches towards a promising design for future super-c omputers. When very high speed computations are needed, data flow mach ines may be relied upon as an adequate solution in which extremely par allel processing is achieved. This paper presents a formal analysis fo r data flow machines. Moreover, the following three machines are consi dered: (1) MIT static data flow machine; (2) TI's DDP static data flow machine; (3) LAU data flow machine. These machines are investigated b y making use of a reference model. The contributions of this paper inc lude: (1) Developing a Data Flow Random Access Machine model (DFRAM), for first time, to serve as a formal modeling tool. Also, by making us e of this model one can calculate the time cost of various static data machines, as well as the performance of these machines. (2) Construct ing a practical Data Flow Simulator (DFS) on the basis of the DFRAM mo del. Such DFS is modular and portable and can be implemented with less sophistication. The DFS is used not only to study the performance of the underlying data flow machines but also to verify the DFRAM model.