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Results: 1-25/140
Authors:
CHERRI AK
HABIB MK
Citation: Ak. Cherri et Mk. Habib, RECODING ALGORITHMS FOR THE MODIFIED SIGNED-DIGIT NUMBERS FOR PARALLEL DIGITAL COMPUTING, Computers & electrical engineering, 24(5), 1998, pp. 279-294
Authors:
BINGULAC S
ALMUTHAIRI NF
Citation: S. Bingulac et Nf. Almuthairi, ON THE EQUIVALENCE BETWEEN MFD MODELS AND PSEUDO-OBSERVABLE FORMS OF MIMO SYSTEMS, Computers & electrical engineering, 24(5), 1998, pp. 295-314
Authors:
GOEL L
Citation: L. Goel, POWER-SYSTEM RELIABILITY COST BENEFIT ASSESSMENT AND APPLICATION IN PERSPECTIVE/, Computers & electrical engineering, 24(5), 1998, pp. 315-324
Authors:
KHAN AZ
Citation: Az. Khan, STUDENT TRAINING IN THE UNDERGRADUATE CURRICULUM OF POWER-SYSTEM TRANSIENT STABILITY, Computers & electrical engineering, 24(5), 1998, pp. 325-334
Authors:
SAHANI AK
NAGAR SK
Citation: Ak. Sahani et Sk. Nagar, DESIGN OF DIGITAL CONTROLLERS FOR MULTIVARIABLE SYSTEMS VIA TIME-MOMENTS MATCHING, Computers & electrical engineering, 24(5), 1998, pp. 335-347
Authors:
CHOI YH
KIM YS
Citation: Yh. Choi et Ys. Kim, A FAULT-TOLERANT HIERARCHICAL DIAGNOSTIC NETWORK FOR MASSIVELY-PARALLEL PROCESSING SYSTEMS, Computers & electrical engineering, 24(5), 1998, pp. 349-361
Authors:
CHATTERJEE S
MISRA RB
ALAM SS
Citation: S. Chatterjee et al., A GENERALIZED SHOCK MODEL FOR SOFTWARE-RELIABILITY, Computers & electrical engineering, 24(5), 1998, pp. 363-368
Authors:
BAKER JT
DYMALE R
CARRERAS RA
RESTAINO S
Citation: Jt. Baker et al., DESIGN AND IMPLEMENTATION OF A LOW-COST STARLIGHT OPTICAL TRACKER SYSTEM WITH 500 HZ ACTIVE TIP TILT CONTROL/, Computers & electrical engineering, 24(3-4), 1998, pp. 123-133
Authors:
COLBAUGH R
GLASS K
Citation: R. Colbaugh et K. Glass, DECENTRALIZED ADAPTIVE-CONTROL OF NONHOLONOMIC MECHANICAL SYSTEMS, Computers & electrical engineering, 24(3-4), 1998, pp. 135-165
Authors:
ALIA G
MARTINELLI E
Citation: G. Alia et E. Martinelli, OPTIMAL VLSI COMPLEXITY DESIGN FOR HIGH-SPEED PIPELINE FFT USING RNS, Computers & electrical engineering, 24(3-4), 1998, pp. 167-182
Authors:
LIM HS
CHERAGHI SH
Citation: Hs. Lim et Sh. Cheraghi, AN OPTIMIZATION APPROACH TO SHAPE-MATCHING AND RECOGNITION, Computers & electrical engineering, 24(3-4), 1998, pp. 183-200
Authors:
GAEDE RK
GOLOS F
MCMAHAN MD
KULICK JH
Citation: Rk. Gaede et al., EVALUATION AND PERFORMANCE ANALYSIS OF THE PROCESS CACHE - A PARTITIONED MULTIPROCESS SECONDARY CACHE, Computers & electrical engineering, 24(3-4), 1998, pp. 201-221
Authors:
MACII E
PONCINO M
Citation: E. Macii et M. Poncino, AUTOMATIC SYNTHESIS OF EASILY SCALABLE BUS ARBITERS WITH DYNAMIC PRIORITY ASSIGNMENT STRATEGIES, Computers & electrical engineering, 24(3-4), 1998, pp. 223-228
Authors:
MASMOUDI A
Citation: A. Masmoudi, COMPUTER-BASED INVESTIGATION OF THE LOAD INFLUENCE ON DFSM DRIVE STABILITY, Computers & electrical engineering, 24(3-4), 1998, pp. 229-244
Authors:
EMINOGLU I
ALTAS IH
Citation: I. Eminoglu et Ih. Altas, THE EFFECTS OF THE NUMBER OF RULES ON THE OUTPUT OF A FUZZY-LOGIC CONTROLLER EMPLOYED TO A PM D.C. MOTOR, Computers & electrical engineering, 24(3-4), 1998, pp. 245-261
Authors:
ALWAN NAS
ALHASHEMY BAR
Citation: Nas. Alwan et Bar. Alhashemy, SYSTOLIC DESIGN OF FREQUENCY-DOMAIN BLOCK LMS ADAPTIVE DIGITAL-FILTERS, Computers & electrical engineering, 24(3-4), 1998, pp. 263-275
Authors:
SAHA GK
Citation: Gk. Saha, VIRTUAL N-VERSIONS PROGRAMMING FOR FAULT-TOLERANT COMPUTING, Computers & electrical engineering, 24(3-4), 1998, pp. 277-278
Authors:
SHIBATA T
Citation: T. Shibata, SPECIAL ISSUE ON IMPLEMENTING INTELLIGENCE ON SILICON INTEGRATED-CIRCUITS - PART II - NEW ARCHITECTURES AND ALGORITHMS, Computers & electrical engineering, 24(1-2), 1998, pp. 1-2
Authors:
IWATA M
TERADA H
XU Y
TAKINE T
MURAKAMI K
Citation: M. Iwata et al., FLOW-THRU PROCESSING CONCEPT AND ITS APPLICATION TO SOFT-COMPUTING, Computers & electrical engineering, 24(1-2), 1998, pp. 3-15
Authors:
TAMARU K
KOBAYASHI K
ONODERA H
Citation: K. Tamaru et al., MEMORY-BASED ARCHITECTURE AND ITS IMPLEMENTATION SCHEME NAMED BIT-PARALLEL BLOCK-PARALLEL FUNCTIONAL MEMORY TYPE PARALLEL PROCESSOR BPBP FMPP, Computers & electrical engineering, 24(1-2), 1998, pp. 17-31
Authors:
IKE K
HIROSE K
YASUURA H
Citation: K. Ike et al., A MODULE GENERATOR OF 2-LEVEL NEURON MOS CIRCUITS, Computers & electrical engineering, 24(1-2), 1998, pp. 33-41
Authors:
IRITA T
TSUJITA T
FUJISHIMA M
HOH K
Citation: T. Irita et al., A SIMPLE CHAOS-GENERATOR FOR NEURON ELEMENT UTILIZING CAPACITANCE-NPN-TRANSISTOR PAIR, Computers & electrical engineering, 24(1-2), 1998, pp. 43-61
Authors:
YONEZU H
TSUJI K
SUDO D
SHIN JK
Citation: H. Yonezu et al., SELF-ORGANIZING NETWORK FOR FEATURE-MAP FORMATION - ANALOG INTEGRATED-CIRCUIT ROBUST TO DEVICE AND CIRCUIT MISMATCH, Computers & electrical engineering, 24(1-2), 1998, pp. 63-73
Authors:
MCGINNITY TM
ROCHE B
MAGUIRE LP
MCDAID LJ
Citation: Tm. Mcginnity et al., NOVEL ARCHITECTURE AND SYNAPSE DESIGN FOR HARDWARE IMPLEMENTATIONS OFNEURAL NETWORKS, Computers & electrical engineering, 24(1-2), 1998, pp. 75-87
Authors:
GUO S
PETERS L
Citation: S. Guo et L. Peters, A HIGH-SPEED FUZZY CO-PROCESSOR IMPLEMENTED IN ANALOGUE DIGITAL TECHNIQUE/, Computers & electrical engineering, 24(1-2), 1998, pp. 89-98