SIO2 GATE INSULATOR DEFECTS, SPATIAL DISTRIBUTIONS, DENSITIES, TYPES,AND SIZES

Standard IC processes, as well as those involving the use of ionizing radiation, such as x-ray lithography etc., result in the generation of bulk defects, and interface states in the gate insulator, or underlyi ng substrate, respectively, of insulated gate field effect transistors . Bulk defects are believed to be present as positively and negatively charged electron and hole traps, respectively, as well as neutral hol e and ''large'' and ''small'' neutral electron traps. This paper provi des a perspective of the current state of knowledge about the spatial distributions of large bulk defects, their areal densities, sizes, pos sible interrelationships among them, and the special cases of defects created by ion implanted silicon and oxygen, where knock-on effects ha ve been simulated. It appears that bulk defects may all have their ori gin in neutral hole traps, (so-called E' centers) and that when the in sulator thickness is decreased to about 6-7 nm, defects are either no longer present, or, more likely, are incapable of trapping charge at r oom temperature because trapped carriers can either tunnel to one of t he interfaces, or be annihilated by a reverse process. It appears poss ible also that the precursor of the several types of defects only form s at a ''grown'' silicon-silicon oxide interface. In theory, this woul d make it possible to grow defect free insulators by a combination of deposition and oxidation processes.