DELAY-FAULT DIAGNOSIS IN SEQUENTIAL-CIRCUITS BASED ON PATH TRACING

The goal of fault diagnosis is to identify the causes of device failur es. Different techniques have been proposed for stuck-at fault diagnos is in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first catego ry of circuits, but not for synchronous sequential circuits. So, this paper concerns with delay fault diagnosis iri non-scan circuits. The p rinciple of the proposed method, based on a path tracing algorithm, is first given. Next, new concepts for improving path tracing in the pro posed diagnosis process (identification of self-masking) are also pres ented. As the method is based on path tracing through the sequential c ircuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCA S-89 sequential benchmark circuits are finally discussed.