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Table of contents of journal: *Integration : The VLSI journal

Results: 1-25/122
VLSI DESIGN IN THE 3RD-DIMENSION
Authors: STRICKLAND S ERGIN E KAELI DR ZAVRACKY P
Citation: S. Strickland et al., VLSI DESIGN IN THE 3RD-DIMENSION, Integration, 25(1), 1998, pp. 1-16
THEORETICAL PROPERTIES OF LFSRS FOR BUILT-IN SELF-TEST
Authors: DUFAZA C
Citation: C. Dufaza, THEORETICAL PROPERTIES OF LFSRS FOR BUILT-IN SELF-TEST, Integration, 25(1), 1998, pp. 17-35
ACCURATE AND EFFICIENT POWER SIMULATION STRATEGY BY COMPACTING THE INPUT VECTOR SET
Authors: TSUI CY PEDRAM M
Citation: Cy. Tsui et M. Pedram, ACCURATE AND EFFICIENT POWER SIMULATION STRATEGY BY COMPACTING THE INPUT VECTOR SET, Integration, 25(1), 1998, pp. 37-52
SYSTOLIC-BASED PARALLEL ARCHITECTURE FOR THE LONGEST COMMON SUBSEQUENCES PROBLEM
Authors: LUCE G MYOUPO JF
Citation: G. Luce et Jf. Myoupo, SYSTOLIC-BASED PARALLEL ARCHITECTURE FOR THE LONGEST COMMON SUBSEQUENCES PROBLEM, Integration, 25(1), 1998, pp. 53-70
AN ALGORITHM FOR FINDING A NONTRIVIAL LOWER-BOUND FOR CHANNEL ROUTING
Authors: PAL RK PAL SP PAL A
Citation: Rk. Pal et al., AN ALGORITHM FOR FINDING A NONTRIVIAL LOWER-BOUND FOR CHANNEL ROUTING, Integration, 25(1), 1998, pp. 71-84
A NEW APPROACH FOR THE DESIGN OF LINEAR SYSTOLIC ARRAYS FOR COMPUTING3RD-ORDER CUMULANTS (VOL 24, PG 1, 1997)
Authors: ALOQEELY MA ALTURAIGI MA ALSHEBEILI SA
Citation: Ma. Aloqeely et al., A NEW APPROACH FOR THE DESIGN OF LINEAR SYSTOLIC ARRAYS FOR COMPUTING3RD-ORDER CUMULANTS (VOL 24, PG 1, 1997), Integration, 25(1), 1998, pp. 85-87
STATE ASSIGNMENT BASED ON 2-DIMENSIONAL PLACEMENT AND HYPERCUBE MAPPING
Authors: LIU S PEDRAM M DESPAIN AM
Citation: S. Liu et al., STATE ASSIGNMENT BASED ON 2-DIMENSIONAL PLACEMENT AND HYPERCUBE MAPPING, Integration, 24(2), 1997, pp. 101-118
OVERCOMING CHIP-TO-CHIP DELAYS AND CLOCK SKEWS
Authors: EVEN G LITMAN A
Citation: G. Even et A. Litman, OVERCOMING CHIP-TO-CHIP DELAYS AND CLOCK SKEWS, Integration, 24(2), 1997, pp. 119-133
ON RETIMING FOR FPGA LOGIC MODULE MINIMIZATION
Authors: CHEN YP WONG DF
Citation: Yp. Chen et Df. Wong, ON RETIMING FOR FPGA LOGIC MODULE MINIMIZATION, Integration, 24(2), 1997, pp. 135-145
A GRAPH-THEORETIC APPROACH TO FEED-THROUGH PIN ASSIGNMENT
Authors: CHEN YP WONG DF
Citation: Yp. Chen et Df. Wong, A GRAPH-THEORETIC APPROACH TO FEED-THROUGH PIN ASSIGNMENT, Integration, 24(2), 1997, pp. 147-158
MODELING AND DESIGNING SILICON THIN-FILM INDUCTORS AND TRANSFORMERS USING HSPICE FOR RFIC APPLICATIONS
Authors: VALKODAI A MANKU T
Citation: A. Valkodai et T. Manku, MODELING AND DESIGNING SILICON THIN-FILM INDUCTORS AND TRANSFORMERS USING HSPICE FOR RFIC APPLICATIONS, Integration, 24(2), 1997, pp. 159-171
A NEW APPROACH FOR THE DESIGN OF LINEAR SYSTOLIC ARRAYS FOR COMPUTING3RD-ORDER CUMULANTS
Authors: ALOQEELY MA ALTURAIGI MA ALSHEBEILI SA
Citation: Ma. Aloqeely et al., A NEW APPROACH FOR THE DESIGN OF LINEAR SYSTOLIC ARRAYS FOR COMPUTING3RD-ORDER CUMULANTS, Integration, 24(1), 1997, pp. 1-17
RTL VERIFICATION OF TIMED ASYNCHRONOUS AND HETEROGENEOUS SYSTEMS USING SYMBOLIC MODEL CHECKING
Authors: VAKILOTOJAR V BEEREL PA
Citation: V. Vakilotojar et Pa. Beerel, RTL VERIFICATION OF TIMED ASYNCHRONOUS AND HETEROGENEOUS SYSTEMS USING SYMBOLIC MODEL CHECKING, Integration, 24(1), 1997, pp. 19-35
A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION, Integration, 24(1), 1997, pp. 37-52
A TIMING-DRIVEN PLACEMENT ALGORITHM WITH THE ELMORE DELAY MODEL FOR ROW-BASED VLSIS
Authors: KOIDE T WAKABAYASHI S ONO M NISHIMARU Y YOSHIDA N
Citation: T. Koide et al., A TIMING-DRIVEN PLACEMENT ALGORITHM WITH THE ELMORE DELAY MODEL FOR ROW-BASED VLSIS, Integration, 24(1), 1997, pp. 53-77
VLSI ARCHITECTURE AND IMPLEMENTATION FOR FS1016 CELP DECODER WITH REDUCED POWER AND MEMORY REQUIREMENTS
Authors: SUEN AN WANG JF LIN JL
Citation: An. Suen et al., VLSI ARCHITECTURE AND IMPLEMENTATION FOR FS1016 CELP DECODER WITH REDUCED POWER AND MEMORY REQUIREMENTS, Integration, 24(1), 1997, pp. 79-97
MIRRORING - A TECHNIQUE FOR PIPELINING SEMI-SYSTOLIC AND SYSTOLIC ARRAYS
Authors: BRAUN M EVEN G WALLE T
Citation: M. Braun et al., MIRRORING - A TECHNIQUE FOR PIPELINING SEMI-SYSTOLIC AND SYSTOLIC ARRAYS, Integration, 23(2), 1997, pp. 115-130
A BDD-BASED VERIFICATION METHOD FOR LARGE SYNTHESIZED CIRCUITS
Authors: VANEIJK CAJ
Citation: Caj. Vaneijk, A BDD-BASED VERIFICATION METHOD FOR LARGE SYNTHESIZED CIRCUITS, Integration, 23(2), 1997, pp. 131-149
ACCURACY AND FIDELITY OF FAST NET LENGTH ESTIMATES
Authors: GANLEY JL
Citation: Jl. Ganley, ACCURACY AND FIDELITY OF FAST NET LENGTH ESTIMATES, Integration, 23(2), 1997, pp. 151-155
SERIAL DIAGNOSTIC FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS
Authors: CHEN SC JOU JM
Citation: Sc. Chen et Jm. Jou, SERIAL DIAGNOSTIC FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS, Integration, 23(2), 1997, pp. 157-170
CONTENT-ADDRESSABLE MEMORY CORE CELLS - A SURVEY
Authors: SCHULTZ KJ
Citation: Kj. Schultz, CONTENT-ADDRESSABLE MEMORY CORE CELLS - A SURVEY, Integration, 23(2), 1997, pp. 171-188
A UNIFIED APPROACH FOR SCHEDULING AND ALLOCATION
Authors: MORENO R HERMIDA R FERNANDEZ M MECHA H
Citation: R. Moreno et al., A UNIFIED APPROACH FOR SCHEDULING AND ALLOCATION, Integration, 23(1), 1997, pp. 1-35
SCHEDULING WITH MULTIPLE VOLTAGES
Authors: RAJE S SARRAFZADEH M
Citation: S. Raje et M. Sarrafzadeh, SCHEDULING WITH MULTIPLE VOLTAGES, Integration, 23(1), 1997, pp. 37-59
HOW GOOD ARE SLICING FLOORPLANS
Authors: YOUNG FY WONG DF
Citation: Fy. Young et Df. Wong, HOW GOOD ARE SLICING FLOORPLANS, Integration, 23(1), 1997, pp. 61-73
A COMPLETE TESTING STRATEGY BASED ON INTERACTING AND HIERARCHICAL FSMS
Authors: FUMMI F SCIUTO D
Citation: F. Fummi et D. Sciuto, A COMPLETE TESTING STRATEGY BASED ON INTERACTING AND HIERARCHICAL FSMS, Integration, 23(1), 1997, pp. 75-93
Risultati: 1-25 | 26-50 | 51-75 | 76-100 | >>