ACCURATE AND EFFICIENT POWER SIMULATION STRATEGY BY COMPACTING THE INPUT VECTOR SET

Accurate power estimation of digital CMOS circuit can be obtained by e xplicit simulation. However, power dissipation is input dependent. To obtain an accurate power estimate, a large input vector set has to be used resulting in large simulation time. One solution is to generate a representative vector set of the original input vector set that conta ins only a few thousand vectors which can then be simulated in a reaso nable time. This paper addresses the problem of vector compaction for power simulation. We compact the input vector set such that the statis tical properties which affect the power consumption are preserved. Exp erimental results show that compaction ratio of 100X is achieved with less than 2% average error in the power estimates. (C) 1998 Elsevier S cience B.V. All rights reserved.